1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a bipolar transistor which can be micropatterned and manufactured in self-alignment, and a method of manufacturing the same.
2. Description of the Related Art
High performance bipolar transistors have been demanded in various application fields such as computers and various analog circuits. Recently, in a manufacturing technique for bipolar transistors, a self alignment technique for base and emitter regions has been proposed. An example of this technique is described in Japanese Patent Disclosure No. 61-208872.
FIGS. 1A to 1D are sectional views showing the steps in manufacturing a bipolar transistor by a self alignment technique. As shown in FIG. 1A, an n.sup.+ -type buried layer 2 is formed in a p-type silicon substrate 1, and an n-type silicon layer 3 is epitaxially grown on the p-type silicon substrate 1. Then, an SiO.sub.2 layer 4 is selectively formed in n-type silicon layer 3 to reach the n.sup.+ -type buried layer 2 and n-type silicon layer 3 by, e.g., a LOCOS process. Thereafter, a polycrystalline silicon layer 5a is formed on the entire surface by, e.g., a CVD process. After boron ions are implanted in the polycrystalline silicon layer 5a, predetermined annealing is performed to diffuse the implanted boron ions in the silicon layer 3, thus forming a p-type base region 6. Then, a polycrystalline silicon layer 5b is formed on the polycrystalline silicon layer 5a by the CVD process, thus forming a polycrystalline silicon layer 5 having an increased thickness. Thereafter, boron ions are implanted in the polycrystalline silicon layer 5 so that the layer 5 has a p-type conductivity.
As shown in FIG. 1B, after an SiO.sub.2 layer 7 is formed on the polycrystalline silicon layer 5 by the CVD process, a photoresist layer 8 having a predetermined pattern is formed on the SiO.sub.2 layer 7. Using the photoresist layer 8 as a mask, the SiO.sub.2 layer 7 and the polycrystalline silicon layer 5 are vertically etched in sequence by reactive ion etching (RIE), to form a groove. Thereafter, the photoresist layer 8 is removed. Then, predetermined annealing is performed to activate the boron ions in the polycrystalline silicon layer 5.
As represented by a broken line in FIG. 1C, an SiO.sub.2 layer 9 is formed on the entire surface by the CVD process. Then, the SiO.sub.2 layer 9 is vertically and anisotropically etched by reactive ion etching to remove the SiO.sub.2 layer 9 except for a portion 10 formed on a side wall of the groove.
As shown in FIG. 1D, a polycrystalline silicon layer 11 is formed on the entire surface by the CVD process. An n-type impurity such as As is heavily implanted in a portion of the base region 6, surrounded by the side-wall SiO.sub.2 layer 10, through the polycrystalline silicon layer 11. Then, predetermined annealing is performed to form an emitter region 13. The emitter region 13 is formed in self-alignment with the polycrystalline silicon layer 5, serving as a base connecting electrode, and an inner base region 14. Upon this annealing, a large amount of boron ions contained in the base connecting electrode 5 are diffused in the base region 6 and the silicon layer 3. As a result, p.sup.+ -type graft base region 14 is integrally formed around the inner base region 12. Thereafter, predetermined emitter, base, and collector electrodes are formed, thus forming an npn bipolar transistor.
According to the above-mentioned conventional method, in the step shown in FIG. 1D, annealing is performed in order to diffuse impurities, and p.sup.+ -type graft base region 14 is formed. Therefore, the base-collector capacity is increased due to the presence of the graft base region. As a result, power consumption is increased, and it becomes difficult to achieve high-speed operation. Though the emitter region is formed in self-alignment, opening formed in polycrystalline silicon layer 5 and SiO.sub.2 layer 7 in the step shown in FIG. 1B is limited by a pattern dimension in photolighography. A columnar projection consisting of n-type region 3 and p-type region 6, which are surrounded by SiO.sub.2 layer 4 and formed in the step shown in FIG. 1A becomes larger in size because of mask alignment error. Thus, micro-fabricating of a bipolar transistor is restricted.